The present invention relates to a technology for rescuing such a storage region in any one of a plurality of nonvolatile memories that encounters a fault occurring time-wise in a nonvolatile storage system that has these memories, for example, to such a technology that is effectively applicable to such a memory card as an Advanced Technology attachment (ATA) memory card mounted with a flash memory.
An electrically rewritable nonvolatile memory such as a flash memory stores information based on a threshold voltage, which varies with an amount of electrons or positive holes injected into the floating gate of the memory cells. The properties of such a threshold voltage of the memory cells will deteriorate time-wise as the number of times of rewriting the memory contents increases. Such a deterioration in the properties results in a write-in error being detected in verification. To solve this problem, there has conventionally been provided a rescue technology for replacing a storage region in which a write-in error occurred with another storage region.
For example, in an ATA memory card used as a file memory, the storage regions of each of nonvolatile memories are divided into such functional sections as a data block regions section, a data-block alternate regions section for rescue, etc. so that each of these functional sections is defined as an aggregate of data blocks given in units of one sector and a corresponding management region. Each of the data blocks is assigned an inherent physical address in each of the memories. If a write-in error occurs in any of these data block regions, a flag indicating the error is set to this region, to set the physical address of such a data block region in said data block alternate regions section that is to substitute for said faulty data block region. Write-in data related to the write-in error is written into a data block of that alternate address. Then, if access is made to the address of said faulty data block, this data block is recognized to be faulty based on the error flag set in its corresponding management region so that access may be made instead to such a data block in the data block alternate regions section that is specified by the alternate address.
The Inventor, however, recognized a problem that in a case where a faulty data block is to be replaced with another only within the corresponding one of a plurality of nonvolatile memories and there is a deviation in fault occurrence ratio among them, if so many write-in errors occur in any one of these memories that cannot be accommodated by the rescue capacity of the data block alternate data block regions section in this memory, the entire relevant memory card must be treated as being faulty.
Concerning this, there have been disclosed such a conventional technology of having a preliminary nonvolatile memory for a backup purpose that is disclosed in JP-A-3-25798 and such a method for processing data necessary to replace a faulty nonvolatile memory that is disclosed in JP-A-9-200636.
The conventional technologies, however, are based on a premise that a faulty nonvolatile memory is to be replaced or a redundant (spare) nonvolatile memory and so are yet to fully utilize the storage regions of each of nonvolatile memories without replacing a faulty one of them.
In view of the above, it is an object of the present invention to provide a nonvolatile storage system that can improve redressing efficiency for a write-in error occurring as time passes by without replacing a faulty one of nonvolatile memories or using a spare nonvolatile memory in the system.
It is another object of the present invention to provide a nonvolatile storage system that can avoid an overall failure thereof without replacing a faulty one of nonvolatile memories or using a spare nonvolatile memory in the system even if a faulty data block cannot be replaced within any one of these memories.
It is a further object of the present invention to provide a nonvolatile storage system that can utilize the storage regions of each nonvolatile memory without waste when replacing a faulty data block.
The typical contents of the present invention in this application are outlined as follows.
(1) Inter-chip alternate: A nonvolatile storage system according to the present invention comprises a plurality of nonvolatile memories capable of read-out, erasure, and write-in operations and a control unit for controlling the operations of these nonvolatile memories in response to an external request. When having detected a write-in error on an operation-subject one of said plurality of nonvolatile memories, said control unit can set inter-chip alternate information about a fact that a storage region related to the write-in error has been replaced by a storage region in another one of said plurality of nonvolatile memories to the nonvolatile memory related to this error and also, when having received inter-chip alternate information from the current operation-subject nonvolatile memory, can switch the operation-subject memory from it to such another nonvolatile memory that is indicated by the chip alternate information. In the present specification, a write-in error refers to a state where when a write-in voltage is applied to a nonvolatile memory (programming) to then verify it, a predetermined threshold voltage cannot be obtained or a state where when the write-in subject is replaced already, confirmation of whether a alternate destination address can be obtained before start of said programming and programming verification finds that it is impossible.
It is thus possible, in inter-chip alternate, to redress a write-in error which occurred at one nonvolatile memory by using a storage region of another nonvolatile memory. This makes it possible, if a faulty data block cannot be replaced with another within one of a plurality of nonvolatile memories, to avoid an overall system error without replacing the faulty nonvolatile memory or using a preliminary nonvolatile memory.
If a write-in error occurred in a nonvolatile memory in which the number of the remaining storage regions capable of new placement has decreased to a predetermined number or less, preferably inter-chip alternate is allowed to that memory. It is thus possible to enable inter-chip alternate so as to eliminate waste of the data blocks as much as possible. That is, by starting inter-chip alternate before such a nonvolatile memory appears that is exhausted to such an extent that intra-chip alternate is no longer possible, the remaining regions capable of new alternate hardly have a large deviation among themselves, thus making it possible to minimize the number of processing cycles required for inter-chip alternate and intra-chip alternate. This is because, if there is a large deviation in the number of the regions capable of new alternate among nonvolatile memories, the number of such nonvolatile memories of these that can be adopted as a alternate destination is decreased, to increase the number of times of making retrieval retrials for looking for such a nonvolatile memory that can be adopted as an inter-chip alternate destination.
To enable inter-chip alternate so as to eliminate waste in the data blocks, inter-chip alternate can be allowed for a write-in error which occurred in a nonvolatile memory in which the number of the storage regions that can be adopted as a alternate destination has been decreased to a predetermined number of less.
A write-in error that occurred in such a nonvolatile memory that is capable of alternate can be accommodated by intra-chip alternate. For example, if a write-in error occurred in a nonvolatile memory which has the storage regions capable of alternate as many as a predetermined number or more, said control unit sets intra-chip alternate information indicating that a storage region related to the write-in error has been replaced with another storage region to such a nonvolatile memory that has the storage region related to this error and also makes it possible to obtain the intra-chip alternate information from an operation-subject nonvolatile memory to then change the operation subject from it to such a storage region that is indicated by this intra-chip alternate information.
It is thus possible to improve the rescue efficiency for write-in errors occurring time-wise without replacing a faulty nonvolatile memory or using a preliminary nonvolatile memory, thus utilizing the storage regions of each of the nonvolatile memories without waste in alternate of faulty data blocks.
Note here that of course a storage region used for said inter-chip or intra-chip alternate is different from a redundant storage region used for defect rescue in a device process.
As a candidate for a alternate destination nonvolatile memory used in inter-chip alternate, such a nonvolatile memory can be adopted that has the remaining storage regions that can be adopted as a alternate destination as many as a number larger than a predetermined number. If there is none of said candidates that can be adopted, another candidate can be adopted that has the storage regions that can be adopted as a alternate destination as many as the predetermined number or less. If a write-in error occurred in a storage region, preferably the operation of writing such data that is related to the write-in error into such a region that substitutes for this storage region related to the write-in error does not compete with an operation of writing other data, which can be made possible when the writing operation is best performed to the nonvolatile memory where this write-in error occurred.
(2) Interleaved writing: In a case where in the above-mentioned nonvolatile storage system said control unit can control interleaved writing for responding to a data write-in request from an external device to thereby sequentially write write-in data in units of a predetermined data quantity into a plurality of nonvolatile memories as shifting the operation timing, when having detected a write-in error during an interleaved writing operation, as another nonvolatile memory that substitutes for a storage region related to the write-in error, it excludes such a series of nonvolatile memories including a nonvolatile memory where said write-in error occurred that are made a subject for interleaved writing.
By doing so, the operation of writing data related to a write-in error into a alternate region can be prevented from competing with an interleaving operation of writing sub-divided other data. At least, such competition can be eliminated easily at a high probability.
From another detailed aspect on interleaved writing, when having detected a write-in error during the interleaved writing operation, as another nonvolatile memory that substitutes for a storage region related to the write-in error, said control unit may select the first candidate from among such nonvolatile memories that are each distant in interleaving order from the preceding and following ones by a predetermined number of two or more.
If said first candidate cannot be selected, said control unit may select such a second candidate that can be adopted as a alternate destination from among such nonvolatile memories of those outside a range in which said first candidate is selected that follow said first candidate in interleaving order.
If said second candidate cannot be selected, said control unit adopts as a third candidate for a alternate destination a nonvolatile where a write-in error occurred.
If said third candidate cannot be selected, said control unit selects such a fourth candidate that can be adopted as a alternate destination from among such nonvolatile memories of those outside the range in which said first candidate is selected that precede said first candidate in interleaving order.
(3) Parallel writing: When parallel writing is used in place of interleaved writing, said control unit can control parallel wiring for responding to a data write-in request from an external device to thereby write write-in data in units of predetermined data quantity to a plurality of nonvolatile memories concurrently, so that when having detected a write-in error during parallel writing, it selects the first candidate for another nonvolatile memory that substitutes for a storage region related to said write-in error, from a range excluding the parallel-writing subject nonvolatile memories including the nonvolatile memory where said write-in error occurred.
(4) The following will describe a nonvolatile memory related to the present invention from a further aspect. A nonvolatile storage system comprises a control unit and a plurality of nonvolatile memories. Said control unit receives data and address information from an external device to then control the storing of the data received from said external device into said plurality of nonvolatile memories, the reading out of the data thus stored in said nonvolatile memories, and the erasing of the data stored in said nonvolatile memories, while said nonvolatile memories each respond to an operation instruction from the control unit to thereby perform a write-in operation of storing data supplied from said control unit, a read-out operation of reading the stored data and supplying it to the control unit, and an erasure operation of erasing the stored data. The control unit then sub-divides the data received from the external device into data portions of a predetermined size and performs an interleaving operation of supplying the first nonvolatile memory with the first one of thus sub-divided data portions together with a write-in operation instruction and supplying the second nonvolatile memory with the second data portion together with a write-in operation instruction while data is being written to the first nonvolatile memory, thus sequentially supplying all of these sub-divided data portions to the plurality of nonvolatile memories. If a write-in error occurred while predetermined data is being written to any one of the plurality of nonvolatile memories, when having detected the write-in error, the control unit controls data storage in supplying said predetermined data together with a write-in operation instruction to the nonvolatile memory engaged in the write-in operation and also to other nonvolatile memories except those to which sub-divided data portions are to be written after the occurrence of the write-in error.
The nonvolatile memories each have a plurality of memory cells, a plurality of word lines, and a plurality of bit lines. Said plurality of memory cells are positioned at the respective intersections between the corresponding word lines and bit lines. The memory cells connected to the respective word lines are classified into, for example, a first group and a second group so that the memory cells of the first group may be used for storing the data supplied from the control unit and the memory cells of the second group may be used for storing predetermined information. The predetermined information contains such information that indicates whether a write-in error occurred when the predetermined data was being stored into any memory cell connected to the relevant word line during the write-in operation and such information that indicates a nonvolatile memory that stored the predetermined data when the write-in error occurred.
The predetermined size of the sub-divided data portions is, for example, such that they can be stored in any of the memory cells of the first group. The write-in, read-out, and erasure operations are performed for each of said word lines, for example.
The memory cells each store data therein based on a threshold voltage that corresponds, for example, to the data to be stored, while the write-in operation comprises a first operation of changing a threshold voltage for each memory cell to a threshold voltage that corresponds to data to be stored and a second operation of confirming whether the threshold voltage for each memory cell has been changed to the corresponding threshold voltage and repeats the first and second operations. In this operation, the write-in error is detected when it is detected that after the first and second operations are repeated a predetermined number of times, the threshold voltage of at least one memory cell has not been changed to the corresponding threshold voltage.
When the write-in error is detected in the write-in operation, the nonvolatile memory posts the occurrence of the write-in error to the control unit, which in turn gives a write-in operation instruction to the other nonvolatile memories after writing data to the relevant nonvolatile memory where the write-in error occurred by specifying a word line different from that involved in writing when the write-in error occurred.
If rescued by redundant means at the stage of a device process, said nonvolatile memory notifies said control unit of the occurrence of a write-in error after writing data through the redundant means by specifying a word line different from that involved in writing when said write-in error occurred.
The above-mentioned and other objects and the novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.